View 843003AG_8069355.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer ics843003 idt? / ics? lvpecl frequency synthesizer 1 ics843003AG rev. a october 23, 2008 general description the ics843003 is a 3 differential output lvpecl synthesizer designed to generate ethernet refer- ence clock frequencies and is a member of the hiperclocks? family of high performance clock solutions from idt. using a 31.25mhz or 26.041666mhz, 18pf parallel resonant crystal, the following frequencies can be generated base d on the settings of 4 fre- quency select pins (div_sel[a1:a0], div_sel[b1:b0]): 625mhz, 312.5mhz, 156.25mhz, and 125mhz. the 843003 has 2 output banks, bank a with 1 differentia l lvpecl output pa ir and bank b with 2 differential lvpecl output pairs. the two banks have their own dedicated frequency select pins and can be independently set for t he frequencies mentioned above. the ics843003 uses idt?s 3 rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter, easily meeting ethernet jitter re quirements. the ics843003 is packaged in a small 24-pin tssop package. features ? three 3.3v lvpecl outputs on two banks, a bank with one lvpecl pair and b bank with 2 lvpecl output pairs ? using a 31.25mhz or 26.041666 crystal, the two output banks can be independently set for 625mhz, 312.5mhz, 156.25mhz or 125mhz ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? vco range: 560mhz ? 700mhz ? rms phase jitter @ 156.25mhz (1.875mhz - 20mhz): 0.51ps (typical) offset noise power 100hz ................ -96.8 dbc/hz 1khz .................. -119.1 dbc/hz 10khz ................ -126.4 dbc/hz 100khz .............. -127.0 dbc/hz ? full 3.3v supply mode ? 0c to 70c ambient operating temperature ? industrial temperature available upon request ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s pin assignment ics843003 24-lead tssop 4.4mm x 7.8mm x 0.925mm package body g package 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 div_selb0 vco_sel mr v cco_a qa0 nqa0 oeb oea fb_div v cca v cc div_sela0 div_selb1 v cco_b nqb0 qb0 nqb1 qb1 xtal_sel test_clk xtal_in xtal_out v ee div_sel a1 block diagram 0 1 0 1 phase detector vco 625mhz 0 = 20 (default) 1 = 24 0 0 1 0 1 2 (default) 1 0 4 1 1 5 0 0 1 0 1 2 1 0 4 (default) 1 1 5 fb_div osc qa0 nqa0 qb0 nqb0 qb1 nqb1 2 2 pullup pulldown pulldown:pullup pullup pulldown pulldown pullup pullup:pulldown pullup oea div_sela[1:0] vco_sel test_clk mr oeb div_selb[1:0] fb_div xtal_out xtal_sel xtal_in
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 2 ics843003AG rev. a october 23, 2008 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1 div_selb0 input pulldown division select pin for bank b. default = low. lvcmos/lvttl interface levels. 2 vco_sel input pullup vco select pin. when low, the pll is bypassed and the crystal reference or test_clk (depending on xtal_sel setting) are passed directly to the output dividers. has an internal pullup resistor so the pll is not bypassed by default. lvcmos/lvttl interface levels. 3 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs qx to go low a nd the inverted outputs nqx to go high. when logic low, the internal dividers and the outputs are enabled. has an internal pulldown resistor so the power-up default st ate of outputs and dividers are enabled. lvcmos/lvttl interface levels. 4v cco_a power output supply pin for bank a outputs. 5, 6 qa0, nqa0 output differential output pair. lvpecl interface levels. 7 oeb input pullup output enable bank b. active high output enable. when logic high, the output pair on bank b is enabled. when logic low, the output pair drives differential low (qb0 = low, nqb0 = high). has an internal pullup resistor so the default power-up state of outputs are enabled. lv cmos/lvttl interface levels. 8 oea input pullup output enable bank a. active high output enable. when logic high, the 2 output pairs on bank a are enabled. when logic low, the output pair drives differential low (qa0 = low, nqa0 = high). has an internal pullup resistor so the default power-up state of outputs are enabled . lvcmos/lvttl interface levels. 9 fb_div input pulldown feedback divide select. when low (default), the feedback divider is set for 20. when high, the feedback divider is set for 24. lvcmos/lvttl interface levels. 10 v cca power analog supply pin. 11 v cc power core supply pin. 12 div_sela0 input pullup division select pin for bank a. default = high. lvcmos /lvttl interface levels. 13 div_sela1 input pulldown division select pin for bank a. default = low. lvcmos/lvttl interface levels. 14 v ee power negative supply pin. 15, 16 xtal_out, xtal_in input parallel resonant crystal interface. xtal_o ut is the output, xt al_in is the input. xtal_in is also the overdrive pin if you w ant to overdrive the crystal circuit with a single-ended reference clock. 17 test_clk input pulldown single-ended reference clock input. has an internal pulldown resistor to pull to low state by default. can leave floatin g if using the crystal interface. lvcmos/lvttl interface levels. 18 xtal_sel input pullup crystal select pin. selects between t he single-ended test_clk or crystal interface. has an internal pullup resistor so the crystal inte rface is selected by default. lvcmos/lvttl interface levels. 19, 20 nqb1, qb1 output differential output pair. lvpecl interface levels. 21, 22 nqb01, qb0 output dif ferential output pair. lvpecl interface levels. 23 v cco_b power output supply pin for bank b outputs. 24 div_selb1 input pullup division select pin for bank b. default = high. lvcmos/lvttl interface levels.
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 3 ics843003AG rev. a october 23, 2008 table 2. pin characteristics function tables table 3a. bank a frequency table table 3b. bank b frequency table symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? inputs feedback divider bank a output divider m/n multiplication factor qa0/nqa0 output frequency (mhz) crystal frequency (mhz) div_sela1 div_sela0 fb_div 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 inputs feedback divider bank b output divider m/n multiplication factor qbx/nqbx output frequency (mhz) crystal frequency (mhz) div_selb1 div_selb0 fb_div 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 4 ics843003AG rev. a october 23, 2008 table 3c. output bank configuration select function table table 3d. feedback divider configuration select function table figure 1. oe timing diagram inputs bank a output divider inputs bank b output divider div_sela1 div_sela0 div_selb1 div_selb0 00 1 0 0 1 01 2 0 1 2 10 4 1 0 4 11 5 1 1 5 inputs fb_div feedback divide 020 124 enabled disabled test_clk oea, oeb nqa0, nqbx qa0, qbx
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 5 ics843003AG rev. a october 23, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = v cca = v cco_a = v cco_b = 3.3v 5%, v ee = 0v, t a = 0c to 70c table 4b. lvcmos/lvttl dc characteristics, v cc = v cca = v cco_a = v cco_b = 3.3v 5%, v ee = 0v, t a = 0c to 70c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma 100ma package thermal impedance, ja 70 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 3.465 v v cco_a, v cco_b output supply voltage 3.135 3.3 3.465 v i ee power supply current 158 ma i cca analog supply current 15 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage div_sel[a0:a1], fb_div, div_sel[b0:b1], oea, oeb, vco_sel, xtal_sel, mr -0.3 0.8 v test_clk -0.3 1.3 v i ih input high current test_clk, fb_div, mr, div_sela1, div_selb0 v cc = v in = 3.465v 150 a oea, oeb, vco_sel, xtal_sel, div_selb1, div_sela0 v cc = v in = 3.465v 5 a i il input low current test_clk, fb_div, mr, div_sela1, div_selb0 v cc = 3.465v, v in = 0v -5 a oea, oeb, vco_sel, xtal_sel, div_selb1, div_sela0 v cc = 3.465v, v in = 0v -150 a
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 6 ics843003AG rev. a october 23, 2008 table 4c. lvpecl dc characteristics, v cc = v cca = v cco_a = v cco_b = 3.3v 5%, v ee = 0v, t a = 0c to 70c note 1: outputs termination with 50 ? to v cco_a, _b ? 2v. table 5. crystal characteristics note: characterized using an 18pf parallel resonant crystal. ac electrical characteristics table 6. ac characteristics, v cc = v cca = v cco_a = v cco_b = 3.3v 5%, v ee = 0v, t a = 0c to 70c note 1: defined as skew within a bank of outputs at the same voltages and with equal load conditions. note 2: defined as skew between outputs at the sa me supply voltages and with equal load conditions. measured at the output differential cross points. note 3: please refer to the phase noise plots. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units v oh output high current; note 1 v cco ? 1.4 v cco ? 0.9 a v ol output low current; note 1 v cco ? 2.0 v cco ? 1.7 a v swing peak-to-peak output voltage swing 0.6 1.0 v parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency fb_div = 20 28 31.25 35 mhz fb_div = 24 23.33 26.04166 29.167 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf parameter symbol test conditio ns minimum typical maximum units f out output frequency div_selx[1:0] = 00 560 700 mhz div_selx[1:0] = 01 280 350 mhz div_selx[1:0] = 10 140 175 mhz div_selx[1:0] = 11 112 140 mhz t sk(b) bank skew, note 1 20 ps t sk(o) output skew; note 2, 4 outputs @ same frequency 35 ps outputs @ different frequencies 100 ps t jit(?) rms phase jitter, (random); note 3 625mhz, (1.875mhz ? 20mhz) 0.42 ps 312.5mhz, (1.875mhz ? 20mhz) 0.50 ps 156.25mhz, (1.875mhz ? 20mhz) 0.51 ps 125mhz, (1.875mhz ? 20mhz) 0.52 ps t r / t f output rise/fall time 20% to 80% 250 600 ps odc output duty cycle div_selx[1:0] = 00 40 60 % div_selx[1:0] 00 47 53 %
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 7 ics843003AG rev. a october 23, 2008 typical phase noise at 125mhz 10gb ethernet filter phase noise result by adding a 10gb ethernet filter to raw data raw phase noise data ? ? ? 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.52ps noise power dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m offset frequency (hz)
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 8 ics843003AG rev. a october 23, 2008 typical phase noise at 156.25mhz 10gb ethernet filter phase noise result by adding a 10gb ethernet filter to raw data raw phase noise data ? ? ? 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.51ps noise power dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m offset frequency (hz)
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 9 ics843003AG rev. a october 23, 2008 typical phase noise at 312.5mhz 10gb ethernet filter phase noise result by adding a 10gb ethernet filter to raw data raw phase noise data ? ? ? 312.5mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.50ps noise power dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m offset frequency (hz)
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 10 ics843003AG rev. a october 23, 2008 typical phase noise at 625mhz 10gb ethernet filter phase noise result by adding a 10gb ethernet filter to raw data raw phase noise data ? ? ? 625mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.42ps noise power dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m offset frequency (hz)
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 11 ics843003AG rev. a october 23, 2008 parameter measureme nt information lvpecl output load ac test circuit rms phase jitter output duty cycle/pulse width/period output skew bank skew output rise/fall time scope qx nqx lvpecl v ee v cc, 2v% 1.3v 0.165v - v cca, v cco_a, _b phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t pw t period t pw t period odc = x 100% nqa0, nqb0, nqb1 qa0, qb0, qb1 t sk(o) nqx qx nqy qy nqb0 qb0 nqb1 qb1 t sk(b) clock outputs 20% 80% 80% 20% t r t f v swing
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 12 ics843003AG rev. a october 23, 2008 application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the ics843003 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc, v cca and v cco_x should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 2 illustrates this for a generic v cc pin and also shows that v cca requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v cca pin. figure 2. power supply filtering recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. test_clk input for applications not requiring the use of the test clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the test_clk to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. v cc v cca 3.3v 10 ? 10f .01f .01f
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 13 ics843003AG rev. a october 23, 2008 crystal input interface the ics843003 has been characterized with 18pf parallel resonant crystals. the ca pacitor values shown in figure 3 below were determined using a 31.25mhz or 26.041666mhz 18pf parallel resonant crystal and were chosen to minimize the ppm error. figure 3. crystal input interface lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 4. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be re duced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . figure 4. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 33p c2 27p xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v cc v cc
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 14 ics843003AG rev. a october 23, 2008 termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impeda nce follower outputs that generate ecl/lvpecl compatible ou tputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 15 ics843003AG rev. a october 23, 2008 layout guideline figure 6a shows a schematic example of the ics843003. an example of lvepcl termination is shown in this schematic. additional lvpecl te rmination approaches are shown in the lvpecl termination application note. in this example, an 18 pf parallel resonant 31.25mhz crystal is used. the c1= 27pf and c2 = 33pf are recommended for frequency accuracy. the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. figure 6a. ics843003 schematic example pc board layout example figure 5b shows an example of ics843003 p.c. board layout. the crystal x1 footprint shown in this example allows installation of either surface mount hc49s or through-hole hc49 package. the footprints of other components in this example are listed in the table 7. there should be at least one decoupling capacitor per power pin. the decoupling capacitors should be located as close as possible to the power pins. the layout assumes that the board has clean analog power ground plane. figure 6b. ics843003 pc board layout example table 7. footprint table note: table 7, lists component sizes shown in this layout example. r7 133 c2 33pf set logic input to '0' vcca vcco=3.3v r6 82.5 rd2 1k vcc ru2 not install vdd c8 0.1u c3 10uf r9 133 zo = 50 ohm vdd + - ru1 1k 3.3v r2 10 vcc x1 31.25mhz r4 82.5 u1 ics843003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 div_selb0 vco_sel mr vcco_a qa0 nqa0 oeb oea fb_div vcca vcc div_sela0 div_sela1 vee xtal_out xtal_in test_clk xtal_sel nqb1 qb1 nqb0 qb0 vcco_b div_selb1 + - to logic input pins c7 0.1u set logic input to '1' vcco r5 133 zo = 50 ohm 1 8 p f r10 82.5 c1 27pf vcc=3.3v r8 82.5 r3 133 zo = 50 ohm vcco rd1 not install c4 0.01u logic control input examples zo = 50 ohm c6 0.1u to logic input pins 3.3v reference size c1, c2 0402 c3 0805 c4, c5, c6, c7, c8 0603 r2 0603
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 16 ics843003AG rev. a october 23, 2008 power considerations this section provides information on power dissipa tion and junction temperature for the ics843003. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843003 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 158ma = 547.5mw power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 3 * 30mw = 90mw total power_ max (3.3v, with all outputs swit ching) = 547.5mw + 90mw = 637.5mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the ap propriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer boar d, the appropriate value is 65c/w per table 8below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.638w * 65c/w = 111.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 8. thermal resitance ja for 24 lead tssop, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 70c/w 65 62
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 17 ics843003AG rev. a october 23, 2008 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate worst case power dissipation into the lo ad, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v coo_max ? 1.7v (v cco_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l ] * (v cco_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cco v cco - 2v q1 rl 50
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 18 ics843003AG rev. a october 23, 2008 reliability information table 9. ja vs. air flow table for a 24 lead tssop transistor count the transistor count for ics843003 is: 3767 package outline and package dimension s package outline - g suffix for 24 lead tssop table 10. package dimensions reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 70c/w 65 62 all dimensions in millimeters symbol minimum maximum n 24 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 19 ics843003AG rev. a october 23, 2008 ordering information table 11. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 843003AG ics843003AG 24 lead tssop tube 0 c to 70 c 843003AGt ics843003AG 24 lead tssop 2500 tape & reel 0 c to 70 c 843003AGlf ics843003AGlf ?lead-free? 24 lead tssop tube 0 c to 70 c 843003AGlft ics843003AGlf ?lead-free? 24 lead tssop 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliabilit y or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserv es the right to change any circuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer idt? / ics? lvpecl frequency synthesizer 20 ics843003AG rev. a october 23, 2008 revision history sheet rev table page description of change date a t10 1 11 17 features section - added lead-free bullet. added recommendations for unused input and output pins. ordering information table - added lead-free part number, marking and note. 1/25/06 a t3b 3 14 bank b frequency table - corrected table labeling. added lvcmos to xtal interface section. updated datasheet format. 2/19/08
ics843003 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future netw orks. contact: www.idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia integrated device technology idt (s) pte. ltd. 1 kallang sector, #07-01/06 kolam ayer industrial park singapore 349276 +65 67443356 fax: +65 67441764 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 37885 idteurope@idt.com japan nippon idt kk sanbancho tokyu, bld. 7f, 8-1 sanbancho chiyoda-ku, tokyo 102-0075 +81 3 3221 9822 fax: +81 3 3221 9824

▲Up To Search▲

Price & Availability of 843003AG

	To Download 843003AG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .